1. Technical Field
The present application relates to memory devices, and particularly to 3D array memory devices in which bit lines and common source lines are arranged to provide a simple routing structure.
2. Description of Related Art
As critical dimensions of devices in integrated circuits shrink to the limits of common memory cell technologies, designers look for techniques to stack multiple levels of memory cells to achieve greater storage capacity and lower costs per bit. For example, thin film transistor techniques are applied to charge trapping memory technologies in Lai et al., “A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006; and in Jung et al., “Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30 nm Node,” IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006.
Another structure that provides vertical NAND cells in a charge trapping memory technology is described in Katsumata et al., “Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices,” 2009 Symposium on VLSI Technology Digest of Technical Papers, 2009. The structure described in Katsumata et al. includes a vertical NAND gate, using silicon-oxide-nitride-oxide-silicon (SONOS) charge trapping technology to create a storage site at each gate/vertical channel interface. The memory structure is based on a column of semiconductor material arranged as the vertical channel for the NAND gate, with a lower select gate adjacent the substrate, and an upper select gate on top. A plurality of horizontal word lines is formed using planar word line layers that intersect with the columns, forming a so-called gate-all-around the cell at each layer.
Katsumata et al. has suggested that the structure can be implemented using multiple-bit-per-cell programming technologies. These multiple-bit-per-cell programming technologies require fine control over threshold voltages, making read and program disturb characteristics even more critical. Therefore, even with high-density three-dimensional flash technologies, the density of data storage can be limited.
Because of the complex backend of line (BEOL) routings, low yield and high cost are critical issues in the manufacture of three-dimensional memory.
It is desirable to provide a structure for three-dimensional integrated circuit memory with low manufacturing cost and simple BEOL routings, including reliable, very small memory elements, and high data densities.